1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous dynamic random access memory (DRAM) and method having a test mode in which an automatic refresh operation with respect to memory cell arrays can be performed by an external address.
2. Description of the Related Art
A synchronous DRAM includes main cells and spare cells, i.e., redundant cells for replacing failed cells. The synchronous DRAM also includes a plurality of banks capable of read and write operations, and independently and simultaneously, conducting an automatic refresh operation, where main cells are automatically refreshed.
In a conventional synchronous DRAM, word-lines are accessed by an external address during read and write. During an automatic refresh operation, word-lines are sequentially accessed by internal addresses. An internal address is automatically generated by an internal address counter in response to an external automatic refresh command. Thus, in the conventional synchronous DRAM, when the automatic refresh is performed, only the main cells are accessed to be automatically refreshed, and the spare cells are not accessed and thus not automatically refreshed.
In the conventional art, RAS only refresh (ROR) is performed in the spare cells. However, ROR has different refresh conditions from those of the automatic refresh, so that refresh failure of cells cannot be exactly screened in a test mode.
It is an objective of the present invention to provide a synchronous DRAM in which main cells and spare cells are accessed by an external address. As a result, both main cells and spare cells may be automatically refreshed during a test mode.
It is another objective of the present invention to provide an automatic refresh method for synchronous DRAM in which main cells and spare cells are accessed by an external address. The method may automatically refresh the accessed main and spare cells during a test mode.
According to the present invention, to achieve the first objective, a synchronous DRAM includes a mode register setting circuit which receives an external signal in response to a plurality of control signals. The external signal causes the mode register setting circuit to generate a mode register setting signal, during an automatic refresh operation in a test mode. In response to the activation of the mode register set signal during the automatic refresh operation in the test mode, an address selector selects and outputs an external address to the memory cell array. Alternatively, in response to the deactivation of the mode register set signal, during an automatic refresh operation in a normal mode, the address selector selects and outputs an internal address, which is generated from an internal address counter, to the memory cell array.
During the automatic refresh operation in the test mode, the main cells and the spare cells in the memory cell array are sequentially accessed by the external address.
To achieve the second objective, an automatic refresh method in the test mode of a synchronous DRAM includes a plurality of steps. The illustrative method applies an external signal to activate a mode register set signal. The method also applies a first logic level to the selection pin to select the main cells. When the mode register set signal is activated and the main cells are selected, the method applies an external address and an automatic refresh command from outside the synchronous DRAM to sequentially access and refresh the main cells. The method applies a second logic level to the selection pin to select the spare cells. When the mode register set signal is acted and the spare cells are selected the method applies the external address and the automatic refresh command from outside the synchronous DRAM to sequentially access and refresh the spare cells.